In general, a cache memory includes memory between a shared system memory and execution units of a processor to hold information in a closer proximity to the execution units of the processor. Caches are often identified based on their proximity from execution units of a processor. For example, a first-level (L1) cache may be close to execution units residing on the same physical processor. A computer system may also hold other cache memories, such as, a second level cache and a third level cache which reside on the processor or elsewhere in the computer system.
When a processor issues a load/store request for a data block in a cache memory, the processor checks for the data block in the cache. If the data block is not in the cache, the cache controller issues a request to the main memory, such as, for example, a Dynamic random access memory (DRAM). Upon receiving a response from the main memory, the cache controller allocates the data block into the cache. Often, selection of a cache line to replace with the newly retrieved block of data is based on a time or use algorithm, such as a Least Recently Used (LRU) cache replacement algorithm.
Dynamic random access memory (DRAM) power consumption is increasingly significant to overall platform power. DRAM chips provide several low-power operating modes, which may reduce background power when a DRAM is not servicing any request. While deeper low power modes conserve energy during idle DRAM periods, such low power modes may result in high exit latencies for the DRAM to return to the active mode.